The invention relates to a method of manufacturing a semiconductor device whereby on a surface of a semiconductor body a conductor track of polycrystalline silicon insulated from the surface is formed in a layer of doped polycrystalline silicon provided on a layer of insulating material, and whereby a strip of polycrystalline silicon is formed between an edge of the conductor and a portion of the surface adjoining the edge, after which a semiconductor zone is formed in the semiconductor body through diffusion of dopant from the conductor through the strip.
A strip of polycrystalline silicon with a very small width of, for example, less than 100 nm may be provided between the edge of the insulated conductor and the portion of the surface adjoining this edge. The semiconductor zone formed through diffusion will accordingly be very narrow, having a width of approximately 150 nm. The method may be used, for example, for the manufacture of a bipolar transistor with a very narrow emitter zone, also called ribbon emitter, which is suitable for the amplification of very high-frequency signals.
In practice, the method is particularly suitable for the manufacture of integrated circuits which comprise besides bipolar transistors having a very narrow emitter zone also other semiconductor elements such as field effect transistors. Besides a pattern of conductors from which the narrow semiconductor zones are formed, accordingly, a pattern of conductors may be provided in the layer of polycrystalline silicon which comprises, for example, gate electrodes of field effect transistors.
European Patent Application EP-A-493,853 discloses a method of the kind mentioned in the opening paragraph whereby the conductor is etched into the layer of doped polycrystalline silicon by means of a first etching mask during the formation of the insulated conductor and the strip of polycrystalline silicon. Then the layer of insulating material is etched away next to the edge of the conductor from the surface of the semiconductor body by means of a second etching mask at the area of the semiconductor zone to be formed. Finally, the conductor is provided along its entire edge with the strip of polycrystalline silicon. Wherever the surface is exposed, the strip of polycrystalline silicon is then present between the edge of the conductor and the portion of the surface adjoining this edge. The semiconductor zone will be formed there during a subsequent heat treatment.
When the known method is used in the manufacture of semiconductor devices comprising besides bipolar transistors also field effect transistors, not only the insulated conductors from which the semiconductor zones are formed but also all further conductors are provided in the layer of polycrystalline silicon by means of the first etching mask. During the provision of the strip of polycrystalline silicon, such a strip is accordingly formed not only at the area of the semiconductor zone to be formed at the edge of the conductor, but along all edges of all conductors. As a result, wider conductors are created in the known method wherever this strip is provided along the edges of the conductors. Conductors are formed by the known method with a width which differs from the width as defined by in the etching mask used for etching these conductors into the layer of polycrystalline silicon. This deviation, which may be approximately 0.1 .mu.m on either side of the conductors, so 0.2 .mu.m in total, is inadmissible in the manufacture of semiconductor devices with a high packing density where the conductors are, for example, less than 0.5 .mu.m wide.